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rev. d a ad9058 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. dual 8-bit 50 msps a/ d converter functional block diagram 8 b ? ref a in encode +v ref 8-bit analog- to -digital converter 8-bit analog- to -digital converter +v ref encode a in ? ref 8 a ad9058 2v ref quadrature receiver 8 q lo 8 i ad9058 g g 90 rf general description the ad9058 combines two independent, high performance, 8 -bit analog-to-digital converters (adcs) on a single monolithic ic. combined with an optional on-board voltage reference, the ad9058 provides a cost-effective alternative for systems requiring two or more adcs. dynamic performance (snr, enob) is optimized to pro vide up to 50 msps conversion rates. the unique architecture results in low input capacitance while maintaining high per- formance and low power (<0.5 w/channel). digital inputs and outputs are ttl compatible. performance has been optimized for an analog input of 2 v p-p ( 1 v; 0 v to 2 v). using the on-board 2 v voltage reference, the ad9058 can be set up for unipolar positive operation (0 v to 2 v). this internal voltage reference can drive both adcs. co mmercial (0 c to 70 c) and m ilitary (?5 c to +125 c) temperature range parts are available. parts are supplied in hermetic 48-lead dip and 44-lead ??lead packages. features 2 matched adcs on single chip 50 msps conversion speed on-board voltage reference low power (<1 w) low input capacitance (10 pf) 65 v power supplies flexible input range applications quadrature demodulation for communications digital oscilloscopes electronic warfare radar
rev. d e2e ad9058especifications electrical characteristics [ v s = 5 v; v ref = 2 v (internal); encode = 40 msps; a in = 0 v to 2 v; ev ref = ground, unless otherwise noted.] 1 all specifications apply to either of the two adcs. test ad9058ajd/ajj ad9058akd/akj parameter temp level min typ max min typ max unit resolution 8 8 bits dc accuracy differential nonlinearity 25 ci 0.25 0.65 0.25 0.5 lsb full vi 0.8 0.7 lsb integral nonlinearity 25 ci 0.5 1.3 0.5 1.0 lsb full vi 1.4 1.25 lsb no missing codes full vi guaranteed guaranteed analog input input bias current 25 ci 75 170 75 170 a full vi 340 340 a input resistance 25 ci 12 28 12 28 k input capacitance 25 civ 10 15 1 015 pf analog bandwidth 25 cv 175 175 mhz reference input reference ladder resistance 25 ci 120 170 220 120 170 220 full vi 80 270 80 270 ladder tempco full v 0.45 0.45 / c reference ladder offset 25 ci 8 16 8 16 mv (top) full vi 24 24 mv reference ladder offset 25 ci 8 23 8 23 mv (bottom) full vi 33 33 mv offset drift coefficient full v 50 50 v/ c internal voltage reference reference voltage 25 ci 1.95 2.0 2.20 1.95 2.0 2.20 v full vi 1.90 2.25 1.90 2.25 v temperature coefficient full v 150 150 v/ c power supply rejection ratio (psrr) 25 ci 10 25 10 25 mv/v switching performance maximum conversion rate 2 25 ci 50 50 60 msps aperture delay (t a )25 civ 0.1 0.8 1.5 0.1 0.8 1.5 ns aperture delay matching 25 civ 0.2 0 5 0.2 0.5 ns aperture uncertainty (jitter) 25 cv 10 10 ps, rms output delay (valid) (t v ) 2 25 ci 8 5 8 ns output delay (t v ) tempco full v 16 16 ps/ c propagation delay (t pd ) 2 25 ci 12 12 19 ns propagation delay (t pd ) tempco full v e16 e16 ps/ c output time skew 25 cv 1 1 ns encode input logic 1 voltage full vi 2 2 v logic 0 voltage full vi 0.8 0.8 v logic 1 current full vi 600 600 a logic 0 current full vi 1000 1000 a input capacitance 25 cv 5 5 pf pulsewidth (high) 25 ci 8 8 ns pulsewidth (low) 25 ci 8 8 ns
rev. d e3e ad9058 test ad9058ajd/ajj ad9058akd/akj parameter temp level min typ max min typ max unit dynamic performance transient response 25 cv 2 2 ns overvoltage recovery time 25 cv 2 2 ns effective number of bits (enob) 3 analog input @ 2.3 mhz 25 ci 7.7 7.2 7.7 bits @ 10.3 mhz 25 ci 7.4 7.1 7.4 bits signal-to-noise ratio 3 analog input @ 2.3 mhz 25 ci 48 45 48 db @ 10.3 mhz 25 ci 46 44 46 db signal-to-noise ratio 3 (without harmonics) analog input @ 2.3 mhz 25 ci 48 46 48 db @ 10.3 mhz 25 ci 47 45 47 db second harmonic distortion analog input @ 2.3 mhz 25 ci 58 48 58 dbc @ 10.3 mhz 25 ci 58 48 58 dbc third harmonic distortion analog input @ 2.3 mhz 25 ci 58 50 58 dbc @ 10.3 mhz 25 ci 58 50 58 dbc crosstalk rejection 4 25 civ 60 4 860 dbc digital outputs logic 1 voltage (i oh = 2 ma) full vi 2.4 2.4 v logic 0 voltage (i ol = 2 ma) full vi 0.4 0.4 v power supply 5 +v s supply current full vi 127 154 127 154 ma ev s supply current full vi 27 38 27 38 ma power dissipation full vi 770 960 770 960 mw notes 1 for applications in which +v s may be applied before ev s , or +v s current is not limited to 500 ma, a reverse-biased clamping diode should be inserted between ground and ev s to prevent destructive latch up. see section entitled using the ad9058. 2 to achieve guaranteed conversion rate, connect each data output to ground through a 2 k pull-down resistor. 3 snr performance limits for the 48-lead dip d package are 1 db less than shown. enob limits are degraded by 0.3 db. snr and en ob measured with analog in put signal 1 db below full scale at specified frequency. 4 crosstalk rejection measured with full-scale signals of different frequencies (2.3 mhz and 3.5 mhz) applied to each channel. wi th both signals synchronously encoded at 40 msps, isolation of the undesired frequency is measured with an fft. 5 applies to both a/ss and includes internal ladder dissipation. specifications subject to change without notice.
rev. d ad9058 ? explanation of test levels test level i. 100% production tested. ii. 100% production tested at 25 c, and sample tested at specified temperatures. iii. sample tested only. iv. parameter is guaranteed by design and characterization testing. v. parameter is a typical value only. vi. all devices are 100% production tested at 25 c. 100% production tested at temperature extremes for extended temperature devices; sample tested at temperature extremes for commercial/industrial devices. digital bits +v s equivalent digital outputs 5v encode 13k equivalent encode circuit ad9058 encode ** a in ** ? ref +v s ? s ?.2v +5v ground comp +v ref +v int d 0 ? 7 * +v s ** indicates each pin is connected through 100 * indicates each pin is connected through 2k 0.1 f burn-in connections absolute maximum ratings 1 analog input . . . . . . . . . . . . . . . . . . . . . . . . ?.5 v to +2.5 v +v s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 v ? s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.8 v to ? v 2 digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . ?.5 v to +v s digital output current . . . . . . . . . . . . . . . . . . . . . . . . 20 ma voltage reference current . . . . . . . . . . . . . . . . . . . . . . 53 ma +v ref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 v ? ref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?.5 v operating temperature range ad9058ajd/ajj/akd/akj . . . . . . . . . . . . . . . 0 c to 70 c maximum junction temperature 3 ad9058ajd/ajj/akd/akj . . . . . . . . . . . . . . . . . . . 150 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . . 300 c notes 1 absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability is not necessarily implied. exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 for applications in which +v s may be applied before ? s , or +v s current is not limited to 500 ma, a reverse-biased clamping diode should be inserted between ground and v s to prevent destructive latch up. see section entitled ?sing the ad9058. 3 typical thermal impedances: 44-lead hermetic j-leaded ceramic package: ja = 86.4 c/w; jc = 24.9 c/w; 48-lead hermetic: dip ja = 40 c/w; jc = 12 c/w. ordering guide temperature package model range description option 1 ad9058ajj 0 c to 70 c 44-lead j-leaded j-44 ceramic 2 ad9058ajj-reel 0 c to 70 c 44-lead j-leaded j-44 ceramic 2 ad9058akj 0 c to 70 c 44-lead j-leaded j-44 ceramic, ac tested ad9058atj/883 3 ?5 c to +125 c 44-lead j-leaded j-44 ceramic, ac tested ad9058ajd 0 c to 70 c 48-lead ceramic dip d-48 ad9058akd 0 c to 70 c 48-lead ceramic d-48 dip, ac tested ad9058atd/883 3 ?5 c to +125 c 48-lead ceramic d-48 dip, ac tested notes 1 d = hermetic ceramic dip package; j = leaded ceramic package. 2 hermetically sealed ceramic package; footprint equivalent to plcc. 3 for specifications, refer to analog devices military products databook. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9058 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. d ad9058 ? 7 17 18 28 39 29 ground ground 6 +v ref comp nc encode ground ground ground nc ground encode d 7 ( msb) 40 top view (not to scale) ad9058 nc = no connect ground +v int +v ref +v s a in a in +v s +v s +v s ? ref ? s ? ref ? s +v s ? s ? s +v s d 7 ( msb) d 0 ( lsb) d 0 ( lsb) d 6 d 5 d 3 d 4 d 2 d 1 d 1 d 2 d 3 d 4 d 5 d 6 ad9058ajj/akj pinouts top view (not to scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ad9058 nc = no connect ground d 7 ( msb) encode d 6 +v s d 5 ground d 4 ? ref d 3 ? s d 2 nc d 1 a in d 0 ( lsb) +v s ground ground ? s +v ref ground comp +v s +v int +v s +v ref ground ground ? s +v s ground a in d 0 ( lsb) nc d 1 d 2 ? ref d 3 ground d 4 +v s d 5 encode d 6 ground d 7 ( msb) ? s ad9058ajd/akd pinouts pin function descriptions j-lead ceramic dip pin number pin number adc-a adc-b mnemonic function adc-a adc-b 343 +v ref top of internal voltage reference ladder 14 11 44 2 ground analog ground return 15 10 541 +v s positive 5 v analog supply voltage 16 9 640 a in analog input voltage 17 8 739 v s negative 5 v supply voltage 19 6 838 v ref bottom of internal voltage reference ladder 20 5 937 +v s positive 5 v digital supply voltage 22 3 10 36 encode ttl compatible convert command 23 2 11 35 d 7 (msb) most significant bit of ttl digital output 25 48 12?7 34?9 d 6 ? 1 ttl compatible digital output bits 26?1 47?2 18 28 d 0 (lsb) least significant bit of ttl digital output 32 41 19 27 ground digital ground return 21, 24, 33 1, 4, 40 20 26 ? s negative 5 v supply voltage 34 39 21 25 ground analog ground return 35 38 22 24 +v s positive 5 v analog supply voltage 36 37 common pins common pins 1 comp connection for external (0.1 f) 12 compensation capacitor 2+v int internal 2 v reference; can drive 13 +v ref for both adcs pin configurations
rev. d ad9058 e6e theory of operation the ad9058 contains two separate 8-bit analog-to-digital con- verters (adcs) on a single silicon die. the two devices can be operated independently with separate analog inputs, voltage references, and clocks. in a traditional flash converter, 256 input comparators are re quired to make the parallel conversion for 8-bit resolution. this is in marked contrast to the scheme used in the ad9058, as shown in figure 1. unlike traditional flash, or parallel, converters, each of the two adcs in the ad9058 utilizes a patented interpolating archi- tecture to reduce circuit complexity, die size, and input capaci tance. these advantages accrue because, compared to a conventional flash design, only half the normal number of input comparator cells is required to accomplish the conversion. in this unit, each of the two independent adcs uses only 128 (2 7 ) comparators to make the conversion. the conversion for the seven most significant bits (msbs) is performed by the 128 comparators. the value of the least significant bit (lsb) is de termined by interpolation between adjacent comparators in the decoding register. a proprietary decoding scheme processes the comparator outputs and provides an 8-bit code to the output register of each adc; the scheme also minimizes error codes. 8 256 analog in ev ref +v ref interpolating latches decode logic latches 8 128 127 2 1 figure 1. comparator block diagram analog input range is established by the voltages applied at the voltage reference inputs (+v ref and ev ref ). the ad9058 can operate from 0 v to 2 v using the internal voltage reference, or anywhere between e1 v and +2 v using external references. input range is limited to 2 v p-p when using external references. the internal resistor ladder divides the applied voltage reference into 128 steps, with each step representing two 8-bit quanti- za tion levels. comp encode a encode +v int a in a +v s d 0a ( lsb) ev s d 0b ( lsb) d 7a ( msb) a in b d 7b ( msb) ad9058 (j-lead) ev ref a ev ref b encode b +v ref a +v ref b clock analog in a 0.5v analog in b 0.5v 0.1 f 0.1 f +5v e5v 0.1 f e2v +2v ad9617 400 400 20k 200 200 800 800 20k 5 5 0.1 f 10pf 1k 50 (see text) clock 8 8 1n4001 4, 19, 21, 25, 27, 42 74hct 273 74hct 273 40 1 43 3 2 6 38 8 7, 20, 26, 39 28 29 30 31 32 33 34 35 18 17 16 15 14 13 12 11 5, 9, 22, 24, 37, 41 10 36 ad9617 ad707 74hct04 figure 2. ad9058 using internal 2 v voltage reference
rev. d ad9058 e7e ad9618 comp encode a encode a in a +v s d 0a ( lsb) ev s d 0b ( lsb) d 7a ( msb) a in b d 7b ( msb) ad9058 (j-lead) +v ref a +v ref b encode b ev ref a ev ref b clock analog in a 0.125v analog in b 0.125v 0.1 f +5v e5v 0.1 f +5v 400 400 50 50 10k 5 5k 0.1 f 10pf 1k 50k (see text) clock 8 8 1n4001 4, 19, 21, 25, 27, 42 74act 273 74act 273 40 1 8 38 2 6 43 3 7, 20, 26, 39 28 29 30 31 32 33 34 35 18 17 16 15 14 13 12 11 5, 9, 22, 24, 37, 41 10 36 ad9618 74act04 0.1 f rz1 rz2 e1v 1v 150 2n3906 e5v 1/2 ad708 20k 1v 2n3904 10 +5v 150 1/2 ad708 20k ad580 1 3 0.1 f 0.1 f 10k 10k figure 3. ad9058 using external voltage references the on-board voltage reference, +v int , is a band gap reference that has sufficient drive capability for both reference ladders. it provides a 2 v reference that can drive both adcs in the ad9058 for unipolar positive operation (0 v to 2 v). using the ad9058 refer to figure 2. using the internal voltage reference con- nected to both adcs as shown reduces the number of external components required to create a complete data acquisition system. the input ranges of the adcs are positive unipolar in this con figuration, ranging from 0 v to 2 v. bipolar input signals are buffered, amplified, and offset into the proper input range of the adc using a good low distortion amplifier such as the ad9617 or ad9618. the ad9058 offers considerable flexibility in selecting the analog input ranges of the adcs; the two independent adcs can even have different input ranges if required. in figure 3, the ad9058 is shown configured for 1 v operation. the reference ladder offset shown in the specifications table refers to the error between the voltage applied to the +v ref (top) or ev ref (bottom) of the reference ladder and the voltage required at the analog input to achieve a 1111 1111 or 0000 0000 transi- tion. this indicates the amount of adjustment range that must be designed into the reference circuit for the ad9058. the diode shown between ground and ev s is normally reverse- biased and is used to prevent latch-up. its use is recommended for applications in which power supply sequencing might allow +v s to be applied before ev s ; or the +v s supply is not current limited. if the negative supply is allowed to float (the +5 v supply is powered up before the e5 v supply), substantial +5 v s upply current will attempt to flow through the substrate (v s supply con- tact) to ground. if this current is not limited to <500 ma, the part may be destroyed. the diode prevents this potentially destructive condition from occurring. timing refer to the ad9058 timing diagram, figure 4. the ad9058 provides latched data outputs with no pipeline delay. to conserve power, the data outputs have relatively slow rise and fall times. when designing system timing, it is important to observe (1) setup and hold times; and (2) the intervals when data is changing. figure 3 shows 2 k pull-down resistors on each of the d 0 ed 7 output data bits. when operating at conversion rates higher than 40 msps, these resistors help equalize rise and fall times and ease latching the output data into external latches. the 74act logic family devices have short setup and hold times and are the recommended choices for speeds of 40 msps or more. layout to ensure optimum performance, a single low impedance ground plane is recommended. analog and digital grounds should be con- nected together and to the ground plane at the ad9058 device. analog and digital power supplies should be bypassed to ground through 0.1 f ceramic capacitors as close to the unit as possible. for prototyping or evaluation, surface-mount sockets are available from methode electronics, inc. (part no. 213-0320602) for evaluating ad9058 surface- mount packages. to evaluate the
rev. d ad9058 e8e ad9058 in through- hole pcb designs, use the ad9058ajd/akd with individual pin sockets (amp part no. 6-330808-0). alterna- tively, surface- mount ad9058 units can be mounted in a through-hole socket (circuit assembly corporation, irvine, cali- fornia part no. ca-44spc-t). ad9058 applications combining two adcs in a single package is an attractive alterna- tive in a variety of systems when cost, reliability, and space are important considerations. different systems emphasize particular specifications, depending on how the part is used. in high density digital radio communications, a pair of high speed adcs are used to digitize the in-phase (i) and quadrature (q) components of a modulated signal. the signal presented to each adc in this type of system consists of message-dependent amplitudes varying at the symbol rate, which is equal to the sample rates of the converters. t a = aperture time t v = data delay of preceding encode t pd = output propagation delay analog input encode d 0 ed 7 va l id data for ne1 va l id data for n va l id data for n+1 data changing t v t a n n+1 n+2 t pd figure 4. timing diagram figure 5 shows what the analog input to the ad9058 would look like when observed relative to the sample clock. signal-to- noise ratio (snr), transient response, and sample rate are all critical specifications in digitizing this eye pattern. analog input sample clock figure 5. i and q input signals receiver sensitivity is limited by the snr of the system. for the adc, snr is measured in the frequency domain and calculated with a fast fourier transform (fft). the signal-to-noise ratio equals the ratio of the fundamental component of the signal (rms amplitude) to the rms level of the noise. noise is the sum of all other spectral components, including harmonic distortion, but excluding dc. although the signal being sampled does not have a significant slew rate at the instant it is encoded, dynamic performance of the adc and the system is still critical. transient response is the time required for the ad9058 to achieve full accuracy when a step function input is applied. overvoltage recovery time is the interval required for the ad9058 to recover to full accuracy after an overdriven analog input signal is reduced to its input range. time domain performance of the adc is also extremely important in digital oscilloscopes. when a track-/sample-and-hold is used ahead of the adc, its operation becomes similar to that de scribed above for receivers. the dynamic response to high frequency inputs can be de scribed by the effective number of bits (enob). the effective number of bits is calculated with a sine wave curve fit and is expressed as: enob n log error measured error ideal =? ()() [] 2 where n is the resolution (number of bits) and measured error is actual rms error calculated from the converter?s outputs with a pure sine wave applied as the input. maximum conversion rate is defined as the encode (sample) rate at which snr of the lowest frequency analog test signal drops no more than 3 db below the guaranteed limit. harmonic distortion e db 60 55 50 45 40 35 input frequency e mhz 0.1 1 10 100 30 +25 c e55 c +125 c figure 6. harmonic distortion vs. analog input frequency signal-to-noise ratio (snr) e db 55 50 45 40 35 input frequency e mhz 0.1 1 10 100 30 +25 c and +125 c e55 c effective number of bits (enob) 8.0 7.2 6.4 5.5 figure 7. dynamic performance vs. analog input frequency
rev. d ad9058 ? die dimensions . . . . . . . . . 106 mils 108 mils 15 ( 2) mils pad dimensions . . . . . . . . . . . . . . . . . . . . . . . . 4 mils 4 mils metallization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gold backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . none substrate potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . nitride die attach . . . . . . . . . . . . . . . . . . . . gold eutectic (ceramic) bond wire . . . . . . . . . 1 mil?.3 mil, gold; gold ball bonding encode d 7 ( msb) ? ref ? s +v s d 1 d 2 d 3 d 4 d 5 d 6 ground ground ground ground +v s ? s ? s +v s d 0 ( lsb) d 0 ( lsb) ground ground +v ref comp +v int +v ref +v s a in a in +v s encode +v s ? ref ? s d 7 ( msb) d 6 d 5 d 3 d 4 d 2 d 1 mechanical information
rev. d ad9058 ?0 outline dimensions 44-lead ceramic leaded chip carrier ?j-formed leads [jlcc] (j-44) dimensions shown in inches and (millimeters) 40 29 28 18 17 7 39 pin 1 top view 6 0.662 (16.82) 0.628 (15.95) sq 0.700 (17.78) 0.680 (17.27) sq 0.050 (1.27) bsc 0.500 (12.70) 0.492 (12.50) 0.650 (16.51) 0.610 (15.49) 0.023 (0.58) 0.013 (0.33) 0.025 (0.64) min 0.078 (1.98) 0.054 (1.37) 0.135 (3.43) 0.100 (2.54) 0.032 (0.81) 0.020 (0.51) 0.040 (1.02) ref x 45 3 places 0.020 (0.51) ref x 45 bottom view pin 1 index 0.065 (1.65) controlling dimensions are in inches; millimeters dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design 48-lead side-brazed solder lid ceramic dip [dip/sb] (d-48) dimensions shown in inches and (millimeters) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design 48 1 24 25 0.620 (15.75) 0.590 (14.99) pin 1 0.098 (2.49) max 0.005 (0.13) min seating plane 0.023 (0.58) 0.014 (0.36) 0.060 (1.52) 0.015 (0.38) 0.200 (5.08) 0.125 (3.18) 0.070 (1.78) 0.030 (0.76) 0.150 (3.81) min 0.225 (5.72) max 2.424 (63.57) max 0.110 (2.79) 0.090 (2.29) 0.630 (16.00) 0.520 (13.21) 0.015 (0.38) 0.008 (0.20)
rev. d ad9058 ?1 revision history location page 5/03?ata sheet changed from rev. c to rev. d changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 changes to outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6/01?ata sheet changed from rev. b to rev. c edits to electrical characteristics headings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 edits to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 edits to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 edits to pinout captions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 edits to layout section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
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